The analog-to-digital converter is a class of electronic component which is used in a wide variety of applications ranging from instrumentation to communications. The basic function of an ADC is to accept an input which is analog—that is to say, it can have any of a continuous range of values—and provide an output in a digital form—that is to say, the output must lie within a representation of a subset of the natural numbers.
In order to properly carry out their function, the vast majority of ADCs are required to be as nearly as possible, or at least approximately, linear: the output should be directly proportional to the input.
An example of an ADC which requires high linearity is that for a single frequency modulated (FM) radio signal, which requires to be linear over the range of frequency modulation from the base band frequency. In comparison, an ADC used in a wide band receiver requires linearity over a far wider range: the wide band receiver will sample the entire 20 MHz FM relevant radio band, such as, for instance, a 20 MHz FM radio band. In addition, such a wide band receiver may be exposed to the “near-far problem” in that it may receive signals from antennas at widely different distances from the receiver: the ADC should be capable of digitising signals from both the distant and nearby antenna accurately. Relative to ADCs for narrowband applications, an ADC for such a wide band receiver application thus not only needs to have a much larger bandwidth, but also requires a much higher “spurious free dynamic range” (SFDR). To achieve this requires a very high degree of linearity.
Non-linearity in an ADC response can arise due to a variety of factors. In particular, deviations in the actual resistance or capacitance values of manufactured on-chip components such as resistors or capacitors, from the design values, can directly result in non-linearity. These deviations can easily arise due to IC process spread, moreover currents which exceed the (small signal) approximations of transistors may also degrade the linearity. Examples are non-linear circuit parameters in multi-level quantizers and digital to analogue converters (DACs).
In general, the non-linearities of an ADC may be classified into static non-linearities, which manifest themselves for constant input signals, and dynamic non-linearities that only manifest themselves for time-varying signals. Histograms of the digital sample values for a known input signal can characterize ADCs with static non-linearities. However, such tests are inadequate to measure ADCs with dynamic errors like hysteresis.
Historically, addition of a controlled amount of noise to the ADC input, called dithering, has been a popular technique to reduce the non-linearity of ADCs. Dithering is mostly used for suppression of non-linearities in ideal ADCs.
A known method of carrying out linearization of ADCs is to use one of a variety of spectra. Typically such spectra are generated as Fast Fourier Transforms (FFT), but other spectra, such as Discrete Cosine Transforms (DCT) may also be used. For example, Adamo et al in “A//D Converters Nonlinearity Measurement and Correction by Frequency Analysis and Dither,” IEEE Tr. Instrumentation Measurement, Vol. 52, No. 4, August 2003 assumes a polynomial non-linearity in the ADC, for which a single carrier at the ADC input causes a series of harmonics in the ADC output. Based on this assumption, Adamo et al analytically determined the energies of these harmonics.
Dynamic element matching (DEM) is a kind of randomization technique that reduces harmonics and intermodulation products in non-ideal ADCs at the expense of a higher noise floor.
This invention is particularly concerned with sigma delta (ΣΔ) ADCs. ΣΔ modulation is a variation of delta (Δ) modulation: the basic form of the two forms of modulation, as applied to a single stage in an ADC, is shown in FIG. 1. In a Δ modulator, an analogue input signal is quantized in quantizer 2, typically to produce a single bit of the digital output signal, although in some known Δmodulators multiple bits may be produced. The resulting quantized signal is subtracted from the original input signal at the (Σ) adder 1, resulting in a remnant or Δ signal which is equal to the original signal less the quantized (bit) output. This Δ signal is fed back to the quantizer, for the next stage of the ADC conversion. The subsequent quantizer output (of the Δ signal) is integrated along with the original quantized output, by means of integrator 4, and finally the output is filtered in a low pass filter 5. The ΣΔ variation is based on the realisation that integration is a linear operation: that is to say, the integral of (a+b) is equal to (the integral of a)+(the integral of b). And thus the integrator 3′ may be included in the circuit between the adder (Σ) and the quantizer 2.
It is known, for example from the Adamo paper referenced above, to minimise the energy of harmonics in the ADC output signal corresponding to a sine wave ADC input. It is also known to use iteratively the inverses of polynomials. However, these methods require precise knowledge of the input frequency which also needs to fall on the grid of fast Fourier transform (FFT) frequencies corresponding to the sine wave input.
There is thus an ongoing requirement for a linearization method which does not suffer to the same extent from these requirements.